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    Technical program    

[Marlow meeting will be held on July 10]
[PATMOS Steering Committee meeting will be held on July 10]

Wednesday 11

08:00 - 08:45. Registration.

08:45 - 09:00. Opening:

  • Welcome
    Antonio J. Acosta, Jorge Juan-Chico [General Co-Chairs]
  • The PATMOS 2002 Program
    Bertrand Hochet [Program Chair]

09:00 - 09:50. Invited Talk:

  • The First Quartz Electronic Watch
    C . Piguet (CSEM, Switzerland)

09:50 - 11:00. Session 1 - Arithmetics:

  • An Improved Power Macro-Model for Arithmetic Datapath Components
    D. Helms, E. Schmidt, A. Schulz, A. Stammermann, W. Nebel (OFFIS Research Institute, Oldenburg, Germany)
  • Performance Comparison of VLSI Adders Using Logical Effort
    H.Q. Dao, V.G. Oklobdzija (University of California, USA)
  • MDSP: A High Performance Low-Power DSP Architecture
    F. Pessolano, J. Kessels, A. Peeters (Philips Research, Eindhoven, TheNetherlands)

11:00 - 11:30. Coffee-Break.

11:30 - 13:00. Session 2 - Low-Level Modeling and Characterization:

  • Impact of Technology in Power-Grid-Induced Noise
    J.A. Carballo, S.R. Nassif (IBM Austin Research Laboratory, USA)
  • Exploiting Metal Layer Characteristics for Low-Power Routing
    A. Windschiegl, P. Zuber, W. Stechele (University of Technology of Munich, Germany)
  • Crosstalk Measurement Technique for CMOS ICs
    F. Picot, P. Coll (ATMEL Rousset, France), D. Auvergne (LIRMM, Université de Montpellier, France)
  • Instrumentation Set-Up for Instruction Level Power Modeling
    S. Nikolaidis, N. Kavvadias, P. Neofotistos, K. Kosmatopoulos, T. Laopoulos (Aristotle University of Thessaloniki, Greece), L. Bisdounis (INTRACOM S.A., Peania, Greece)

13:00 - 14:30. Lunch.

14:30 - 16:30. Session 3 - Asynchronous and Adiabatic Techniques:

  • Low-Power Asynchronous A/D Conversion
    E. Allier, L. Fesquet, M. Renaudin, G. Sicard (TIMA Laboratory, Grenoble, France)
  • Optimal Two-Level Delay-Insensitive Implementation of Logic Functions
    I. Lemberski, M. Josephs (South Bank University, London, UK)
  • Resonant Multistage Charging of Dominant Capacitances
    C. Saas, J.A. Nossek (Munich University of Technology, Germany)
  • A New Methodology to Design Low-Power Asynchronous Circuits
    O. Garnica, J. Lanchares, R. Hermida (Universidad Complutense de Madrid, Spain)
  • Designing Carry Look-ahead Adders with an Adiabatic Logic Standard-Cell Library
    A. Blotti, M. Castellucci, R. Saletti (University of Pisa, Italy)

16:30 - 17:00. Coffee-Break.

17:00 - 18:00. Poster Session (see contents at the end of the program)

18:00. End of sessions and transfer to the Hotels.

20:00. Reception Cocktail. Guided Tour to the Reales Alcázares.

Thursday 12

09:00 - 9:50. Invited Talk:

  • Clocking and Clocked Storage Elements in Multi-GHz Environment
    V.G. Oklobdzija (University of California, USA)

09:50 - 11:00. Session 4 - CAD Tools and Algorithms:

  • Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment
    T. Mahnke, W. Stechele (Technical University of Munich, Germany), W. Hoeld (National Semiconductor GmbH, Fuerstenfeldbruck, Germany)
  • Transistor Level Synthesis Dedicated to Fast I.P. Prototyping
    A. Landrault, L. Pellier, A. Richard, C. Jay (Infineon Technologies, Sophia Antipolis, France), M. Robert, D. Auvergne (LIRMM, Université de Montpellier, France)
  • Robust SAT-Based Search Algorithm for Leakage Power Reduction
    F.A. Aloul (University of Michigan, USA), S. Hassoun (Tufts University, USA), K.A. Sakallah, D. Blaauw (University of Michigan, USA)

11:00 - 11:30. Coffee-Break.

11:30 - 13:00. Session 5 - Timing:

  • PA-ZSA (Power Aware Zero Slack Algorithm): A Graph Based Timing Analysis for
    Ultra Low-Power CMOS VLSI
    K.W. Choi, A. Chatterjee (Georgia Institute of Technology, Atlanta, USA)
  • A New Methodology for Efficient Synchronization of RNS-based VLSI Systems
    D. González, A. García (Universidad de Granada, Spain), G.A. Jullien (University of Calgary, Canada), J. Ramírez, L. Parrilla, A. Lloris (Universidad de Granada, Spain)
  • Clock Distribution Network Optimization under Self-Heating and Timing Constraints
    M.R. Casu, M. Graziano, G. Masera, G. Piccinini, M.M. Prono, M. Zamboni (Politecnico di Torino, Italy)
  • A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches
    R. Jiménez, P. Parra, P. Sanmartín, A.J. Acosta (Instituto de Microelectrónica de Sevilla, Spain)

13:00 - 14:30. Lunch.

14:30 - 16:00. Session 6 - Gate-Level Modeling:

  • A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers
    J.L. Rosello, J. Segura (Balearic Islands University, Spain)
  • Output Waveform Evaluation of Basic Pass Transistor Structure
    S. Nikolaidis, H. Pournara (University of Thessaloniki, Greece) A. Chatzigeorgiou (University of Macedonia, Thessaloniki, Greece)
  • An Approach to Energy Consumption Modeling in RC Ladder Circuits
    M. Alioto (Universita di Siena, Italy), G. Palumbo, M. Poli (Universita di Catania, Italy)
  • Structure Independent Representation of Output Transition Time for CMOS Library
    P. Maurine, N. Azemard, D. Auvergne (LIRMM, Université de Montpellier, France)

16:00 - 16:30. Coffee-Break.

16:30 - 18:00. Session 7 - Memory Optimization:

  • A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word
    M. Jayapala, F. Barat, P. Op de Beeck (ESAT/ACCA, Heverlee, Belgium), F. Catthoor (IMEC vzw, Heverlee, Belgium), G. Deconinck, H. Corporaal (Delft University of Technology, The Netherlands)
  • Design and Realization of a Low Power Register File Using Energy Model
    Z. Xue-mei, Y. Yi-Zheng (Harbin Institute of Technology, P.R. China)
  • Register File Energy Reduction by Operand Data Reuse
    H. Takamura, K. Inoue, V.G. Moshnyaga (Fukuoka University, Japan)
  • Energy-Efficient Design of the Reorder Buffer
    D. Ponomarev, G. Kucuk, K. Ghose (State University of New York, USA)

18:00. End of sessions and transfer to the Hotels.

20:00. Gala Dinner.

Friday 13

09:00 - 9:50. Invited Talk:

  • Trends in Ultralow-Voltage RAM Technology
    K. Itoh (Central Research Laboratory, Hitachi Ltd., Tokyo, Japan)

09:50 - 11:00. Session 8 - High-level Modeling and Design:

  • Off-Line Data Profiling Techniques to Enhance Memory Compression in Embedded Systems
    L. Benini (Universita di Bologna, Italy), A. Macii, E. Macii (Politecnico di Torino, Italy)
  • Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors
    N.D. Zervas, G. Pagkless (Alma Technologies S.A., Attica. Greece), M. Dasigenis, D. Soudris (Democritus University of Thrace, Greece)
  • Power Consumption Estimation of a C Program for Data-Intensive Applications
    E. Senn, N. Julien, J. Laurent, E. Martin (University of South-Brittany, France)

11:00 - 11:30. Coffee-Break.

11:30 - 13:00. Session 9 - Communications Modeling and Activity Reduction:

  • A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission
    C. Kretzschmar, R. Siegmund, D. Müller (Chemnitz University of Technology, Germany)
  • Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level
    C. Baena, J. Juan, M.J. Bellido, P. Ruiz de Clavijo, C.J. Jiménez, M. Valencia (Instituto de Microelectrónica de Sevilla, Spain)
  • Low-Power FSMs in FPGA: Encoding Alternatives
    G. Sutter, E. Todorovich (Universidad Nacional del Centro, Tandil, Argentina), S. Lopez-Buedo, E. Boemo (Universidad Autónoma de Madrid, Spain)
  • Synthetic Generation of Events for Address-Event-Representation Communications
    A. Linares-Barranco, G. Jiménez, A. Civit (Universidad de Sevilla, Spain), B. Linares-Barranco (Instituto de Microelectrónica de Sevilla, Spain)

13:00 - 13:15. Closing.

13:15 - 14:45. Lunch.

15:00. Transfer to the Hotels.


  • Reducing Energy Consumption via Low-Cost Value Prediction
    T. Sato, I. Arita (Kyushu Institute of Technology, Japan)
  • Dynamic Voltage Scheduling for Real Time Asynchronous Systems
    M. Es Salhiene, L. Fesquet, M. Renaudin (TIMA Laboratory, Grenoble, France)
  • Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level
    P. Ruiz de Clavijo, J. Juan, M.J. Bellido, A. Millán, D. Guerrero (Instituto de Microelectrónica de Sevilla, Spain)
  • Power Efficient Vector Quantization Design Using Pixel Truncation
    K. Masselos, P. Merakos, C.E. Goutis (University of Patras, Greece)
  • Minimizing Spurious Switching Activities in CMOS Circuits
    A. Wroblewski, F. Auernhammer, J.A. Nossek (Munich University of Technology, Germany)
  • Modeling Propagation Delay of MUX, XOR and D-Latch Source-Coupled Logic Gates
    M. Alioto (Universita di Siena, Italy), G. Palumbo (Universita di Catania, Italy)
  • Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines
    G. Cappuccino, G. Cocorullo (University of Calabria, Italy)
  • Selective Clock-Gating for Low Power/Low Noise Synchronous Counters
    P. Parra, A.J. Acosta, M. Valencia (Instituto de Microelectrónica de Sevilla, Spain)
  • Probabilistic Power Estimation for Digital Signal Processing Architectures
    A. Freimann (Universität Hannover, Germany)
  • Modeling of Propagation Delay of a First Order Circuit with a Ramp Input
    R. Mita, G. Palumbo (University of Catania, Italy)
  • Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)
    A. Millán, J. Juan, M.J. Bellido, P. Ruiz de Clavijo, D. Guerrero (Instituto de Microelectrónica de Sevilla, Spain)
  • Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems
    R. Ionita (Polytechnic Institute, Bucharest, Romania), A. Vladimirescu (University of California, USA), P. Jespers (Universite Catholique de Louvain, Belgium)
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[ October 2, 2002 2:34 PM ]